1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to an electrically writable/erasable and programmable ROM (EEPROM).
2. Description of the Prior Art
A column latch circuit of such EEPROM is disclosed in IEEE ISSCC "Digest of Technical Papers", 1985, p. 170.
FIG. 1 is an electric circuit diagram showing a conventional column latch circuit, and FIG. 2 is an electric circuit diagram showing a column latch circuit and high-voltage switches.
Referring to FIGS. 1 and 2, description is now made on the structure of the column latch circuit of the conventional EEPROM. A first voltage V.sub.PP1 is supplied to a high-voltage switch 1, which is formed by enhancement n-channel MOS transistors (hereinafter referred to as transistors) 101 and 102 and a capacitor 103 as shown in FIG. 2. Similarly, a second high-voltage switch 2 is formed by transistors 201 and 202 and a capacitor 203.
A bit line 3 is connected to the first high-voltage switch 1 and a control gate line 4 is connected to the second high-voltage switch 2. Eight such bit lines 3 are provided in case of forming one byte by eight bits, and one such control gate line 4 is provided with respect to eight bit lines 3. The bit line 3 is connected with an inverter 5, which is formed by a transistor 51 and a depletion n-channel MOS transistor 52. That is, the transistor 51 has a gate connected to the bit line 3, a grounded source and a drain connected to the source and the gate of the depletion n-channel MOS transistor 52 as well as to the gate of a transistor 7. The source of the transistor 7 is grounded and the drain thereof is connected to the bit line 3.
The bit line 3 is connected with the drain of a selection gate 11, whose gate is connected with a word line 10. The source of the selection gate 11 is connected to the drain of a memory transistor 10, whose source is grounded. The bit line 3 is further connected with the source of a Y gate 14, which has a gate connected with a Y gate line 13 and a drain connected with an I/O line 16.
The control gate line 4 is connected with an inverter 6 which is formed by a transistor 61 and a depletion MOS transistor 62. That is, the transistor 61 has a gate connected to the control gate line 4 and a grounded source. The drain of the transistor 61 is connected to the source and the gate of the depletion MOS transistor 62, as well as to the gate of a transistor 8. The depletion MOS transistor 62 is supplied in its drain with a first clock signal 9. The control gate line 4 is connected with the drain of the transistor 8, whose source is grounded.
Further, the control gate line 4 is connected with the drain of a selection gate 12, whose gate is connected with the word line 10 and the source thereof is connected to the gate of the aforementioned memory transistor 18. The control gate line 4 is further connected to the source of a Y gate 15, whose gate is connected with the Y gate line 13 and the drain thereof is connected with a CG line 17.
A bit line latch circuit is formed by the first clock signal 9, the transistors 7 and 51 and the depletion MOS transistor 52, and a control gate line latch circuit is formed by the first clock signal 9, the transistors 8 and 61 and the depletion MOS transistor 62. The bit line latch circuit and the control gate line latch circuit are referred to as a column latch circuit in total.
With reference to FIGS. 1 and 2, description is now made on the operation of the column latch circuit. In general, write operation in memory cells of the EEPROM requires an extremely long period of time (several to 10 mesec), differently from that required for a static RAM. Therefore, several to several ten seconds are required in case where a large number of bytes are to be reloaded, contents of the entire chip are to be updated or high integration is achieved. Thus, an EEPROM exceeding 64 Kbits is generally provided with page mode writing for simultaneously performing writing of a plurality of bytes.
In this case, data to be written must be latched per bit line 3 and control gate line 4. The gate of the memory transistor 18 as shown in FIG. 1 is in two-layer structure, in which the lower gate is covered by an insulating layer and called as a floating gate. This floating gate stores positive and negative charges to change the threshold of the memory transistor 18, thereby to store binary data of "0" and "1". An oxide film partially forming an overlapping portion of the floating gate and the drain is made extremely thin so that electrons are tunnelled in the thin oxide film, to be transferred between the floating gate and the drain.
The operation for injecting the electrons into the floating gate thereby to shift the threshold of the memory transistor 18 to a higher value is referred to as erase operation, which is adapted to store the data "1". The operation for extracting the electrons from the floating gate to shift the threshold to a lower value is referred to as program operation, which is adapted to store the data "0". In the erase operation, a high voltage is applied to the word line 10 and the control gate line 4, and the bit line 3 is converted to the ground potential. In the program operation, a high voltage is applied to the word line 10 and the bit line 3, and the control gate line 4 is grounded.
In a recent EEPROM, high voltages required for the erase operation and the program operation are generated on the chip, whose current supplying ability is limited and hence the high voltages are switched by the high-voltage switches 1 and 2. In order to make the bit line 3 rise at a high voltage, the bit line 3 is held substantially at the supply voltage level, the Y gate line 13 is converted to the ground potential, the Y gate 14 is turned off and the high-voltage switch 1 is turned on thereby to supply the first high voltage V.sub.PP1 to the bit line 3.
In order to make the control gate line 4 rise at a high voltage, the control gate line 4 is held substantially at the supply voltage level, the Y gate line 13 is converted to the ground potential, the Y gate 15 is turned off and the high-voltage switch 2 is turned on to supply a second high voltage V.sub.PP2 to the control gate line 4.
In other words, the column latch circuit serves to hold the potential of the control gate line 4 of the byte whose data must be updated substantially at the supply voltage level as well as to hold the bit line 3 of the bit to be written with the data "0" substantially at the supply voltage level.
Description is now made in further detail on the prior art example as shown in FIG. 1. In a write mode, the first clock signal 9 becomes the supply voltage level, whereby the inverters 5 and 6 are respectively activated. A signal of the supply voltage level is applied to the CG line 17 and an inverted signal of the input data is applied to the I/O line 16, whereby the Y gate line 13 of the byte to be written becomes a high level.
When the control gate line 4 becomes a high level, a low-level signal is applied to the gate of the transistor 8, which is then turned off. The second high voltage V.sub.PP2 is thus applied to the control gate line 4 through the high-voltage switch 2, whereby the control gate line 4 rises at a high voltage. When the bit line 3 is at a high level, it also rises at a high voltage on the leading edge of the first high voltage V.sub.PP1. When, however; the bit line 3 is at a low level, a high-level signal is applied to the gate of the transistor 7 which has been turned on, whereby the bit line 3 is held at the low level even if the first high voltage V.sub.pp1 rises, and hence the memory transistor 18 is not programmed.
The conventional EEPROM of the above structure requires the two-system high voltages V.sub.PP1 and V.sub.PP2, while the high-voltage outputs must be switched and the inverters 5 and 6 are required. Provision of the two system high voltages leads to increase in chip area, and the high-voltage outputs cannot be readily switched. Although EEPROMs have been prepared by metal-oxide semiconductors (MOS) in recent years, further, inverters formed by complementary metal-oxide semiconductors (CMOS) lead to increase in chip area, which may cause latch-up phenomenon.